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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM67C518/D
32K x 18 Bit BurstRAMTM Synchronous Fast Static RAM
With Burst Counter and Registered Outputs
The MCM67C518 is a 589,824 bit synchronous static random access memory designed to provide a burstable, high-performance, secondary cache for the i486TM and PentiumTM microprocessors. It is organized as 32,768 words of 18 bits, fabricated with Motorola's high-performance silicon-gate BiCMOS technology. The device integrates input registers, a 2-bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 - A14), data inputs (D0 - D17), and all control signals except output enable (G) are clock (K) controlled through positive-edge-triggered noninverting registers. This device contains output registers for pipeline operations. At the rising edge of K, the RAM provides the output data from the previous cycle. Output enable (G) is asynchronous for maximum system design flexibility. Burst can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM67C518 (burst sequence imitates that of the i486) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. Dual write enables (LW and UW) are provided to allow individually writeable bytes. LW controls DQ0 - DQ8 (the lower bits), while UW controls DQ9 - DQ17 (the upper bits). This device is ideally suited for systems that require wide data bus widths and cache memory. See Figure 2 for applications information. * * * * * * * * * * *
MCM67C518
FN PACKAGE PLASTIC CASE 778-02
PIN ASSIGNMENTS
A6 A7 E UW LW ADSC ADSP ADV K G A8 A9 A10 DQ9 DQ10 VCC VSS DQ11 DQ12 DQ13 DQ14 VSS VCC DQ15 DQ16 DQ17 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 41 14 40 15 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 A5 A4 A3 A2 A1 A0 VSS VCC NC A14 A13 A12 A11 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0
PIN NAMES
A0 - A14 . . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock ADV . . . . . . . . . . . . Burst Address Advance LW . . . . . . . . . . . . Lower Byte Write Enable UW . . . . . . . . . . . . Upper Byte Write Enable ADSC . . . . . . . . . Controller Address Status ADSP . . . . . . . . . Processor Address Status E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 - DQ17 . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . No Connection All power supply and ground pins must be connected for proper operation of the device.
Single 5 V 5% Power Supply Fast Access Time/Fast Cycle Time = 6 ns/100 MHz, 7 ns/80 MHz, 9 ns/66 MHz Byte Writeable via Dual Write Enables Internal Input Registers (Address, Data, Control) Output Registers for Pipelined Applications Internally Self-Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three-State Outputs Common Data Inputs and Data Outputs 3.3 V I/O Compatible High Board Density 52-Lead PLCC Package
BurstRAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp.
REV 3 5/95
(c) Motorola, Inc. 1994 MOTOROLA FAST SRAM
MCM67C518 1
BLOCK DIAGRAM (See Note)
ADV BURST LOGIC Q0 K BINARY COUNTER Q1 ADSC ADSP CLR A1 A0 15 A1 32K x 18 MEMORY ARRAY INTERNAL A0 ADDRESS
2 A0 - A14 ADDRESS REGISTER 15 A1 - A0 A2 - A14 18 9 9
UW LW
WRITE REGISTER
DATA-IN REGISTERS
E
ENABLE REGISTER
9
9
DATA-OUT REGISTERS OUTPUT BUFFER
G DQ0 - DQ8 DQ9 - DQ17 9 9
NOTE: All registers are positive-edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP-initiated two cycle WRITE can be performed by asserting ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write cycle in WRITE CYCLES timing diagram). When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE (See Note)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A14 - A2 A14 - A2 A14 - A2 A14 - A2 A1 A1 A1 A1 A0 A0 A0 A0
NOTE: The burst wraps around to its initial state upon completion.
MCM67C518 2
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E H H L L L X X X X ADSP L X L H H H H H H ADSC X L X L L H H H H ADV X X X X X L L H H UW or LW X X X L H L H L H K L-H L-H L-H L-H L-H L-H L-H L-H L-H Address Used N/A N/A External Address External Address External Address Next Address Next Address Current Address Current Address Operation Deselected Deselected Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means Don't Care. 2. All inputs except G must meet setup and hold times for the low-to-high transition of clock (K). 3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Read Write Deselected G L H X X I/O Status Data Out High-Z High-Z -- Data In High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 1.6 - 10 to + 85 0 to +70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Storage Temperature Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MOTOROLA FAST SRAM
MCM67C518 3
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width 20 ns) for I 20.0 mA. Symbol VCC VIH VIL Min 4.75 2.2 - 0.5* Max 5.25 VCC + 0.3** 0.8 Unit V V V
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (G = VIH) AC Supply Current (G = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time tKHKH min) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) ICCA6 ICCA7 ICCA9 ISB1 VOL Min -- -- -- Max 1.0 1.0 310 290 275 75 0.4 Unit A A mA
-- --
mA V
VOH 2.4 3.3 V NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance (All Pins Except DQ0 - DQ17) Input/Output Capacitance (DQ0 - DQ17) Symbol Cin CI/O Typ 4 6 Max 5 8 Unit pF pF
MCM67C518 4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5% TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM67C518-6 Parameter Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Address Address Status Data In Write Address Advance Chip Enable Address Address Status Data In Write Address Advance Chip Enable Symbol tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tADSVKH tDVKH tWVKH tADVVKH tEVKH tKHAX tKHADSX tKHDX tKHWX tKHADVX tKHEX Min 10 -- -- 2 2 0 -- 2 4 4 2.5 Max -- 6 5 -- -- -- 6 6 -- -- -- MCM67C518-7 Min 12.5 -- -- 2 2 0 -- 2 5 5 2.5 Max -- 7 5 -- -- -- 6 6 -- -- -- MCM67C518-9 Min 15 -- -- 2 2 0 -- 2 5 5 2.5 Max -- 9 6 -- -- -- 6 6 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns 7 6 5 Notes
Hold Times:
0.5
--
0.5
--
0.5
--
ns
7
NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP high for the setup and hold times. 3. All read and write cycle timings are referenced from K or G. 4. G is a don't care when UW or LW is sampled low. 5. Maximum access times are guaranteed for all possible i486 and Pentium external bus cycles. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled.
AC TEST LOADS
+5V 480 OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM67C518 5
READ CYCLES
MCM67C518 6
t KLKH t KHKL t KHADSX t ADSVKH A2 ADSP STARTS NEW READ A3 CHIP DESELECT A4 t KMWX t WVKH t ADWKH t KHADVX t GLQV (ADV SUSPENDS BURST) t GLQX t GHQZ Q(A1) SINGLE READ Q(A2) t KHQV t KHQX2 Q(A2 +1) Q(A2 + 2) BURST READ (BURST WRAPS AROUND TO ITS INITIAL STATE) Q(A2 + 3) Q(A2) Q(A2 +1) t KHQZ Q(A3)
t KHKH
K
t ADSVKH
t KHADSX
ADSP
ADSC
t AVKH
t KNAX
A
A1
LW, UW
t EVKH
t KHEX
E
ADV
G
t KHQV
t KHQX1
MOTOROLA FAST SRAM
Q
WRITE CYCLES
t KHKH
K t KHKL t KHADSX t KLKH
t ADSVKH
MOTOROLA FAST SRAM
t ADSVKH t KHADSX ADSC STARTS NEW BURST t KHAX A1 W IS IGNORED FOR FIRST CYCLE WHEN ADSP INITIATES BURST A2 A3 t WVKH t KHEX t ADVVKH ADV SUSPENDS BURST t DVKH D(A1) t GHQZ D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) SINGLE WRITE BURST WRITE (WITH A SUSPENDED CYCLE) NEW BURST WRITE
ADSP
ADSC
t AVKH
ADDRESS
t KHWX
LW, UW
t EVKH
E t KHADVX
ADV
G t KHDX
DATA IN
D(A3 + 2)
DATA OUT
Q(An - 1)
Q(An)
MCM67C518 7
BURST READ
MCM67C518 8
COMBINATION READ/WRITE CYCLES (E low, ADSC high)
t KHKH t KLKH t KHKL A1 t KHWX t WVKH A2 A3 t KHADVX t ADVKH t KHDX t DVKH D(A2) t KHQV t GHQZ Q(A1) t GLQX t KHQV t KHQX2 Q(A3) Q(A3 + 1) Q(A3 + 2) READ WRITE BURST READ
K
t KHADSX
t ADVSKH
ADSP
t AVKH t KHAX
A
LW, UW
ADV
G
D
t KHQX1
MOTOROLA FAST SRAM
Q
APPLICATION EXAMPLE
DATA BUS DATA ADDRESS BUS ADDRESS 15 CLOCK PentiumTM 72
ADDR CLK K CACHE CONTROL LOGIC
ADDR K ADSC W G ADV
DATA
MCM67C518
ADSP
ADS CONTROL
256K Byte Burstable, Secondary Cache Using Four MCM67C518FN7s With a 75 MHz (bus speed) Pentium Figure 2
MOTOROLA FAST SRAM
MCM67C518 9
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
67C518
XX
X
Speed (6 = 6 ns, 7 = 7 ns, 9 = 9 ns) Package (FN = PLCC)
Full Part Numbers -- MCM67C518FN6
MCM67C518FN7
MCM67C518FN9
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM67C518 10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE 52-LEAD PLCC CASE 778-02
B -NY BRK D -L52 LEADS ACTUAL -MW D V A Z R 0.007 (0.180)
M
0.007 (0.180) U
M
T L -M
M
S
N
S
0.007 (0.180)
T L -M
S
N
S
Z
(NOTE 1) 52
1
X VIEW D-D 0.007 (0.180)
M
G1 0.010 (0.250)
S
T L -M
S
N
S
T L -M
S
N
S
T L -M
S
N
S
H
0.007 (0.180)
M
T L -M
S
N
S
C
(NOTE 1) 52
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1 K F VIEW S 0.007 (0.180)
M
J
-T-
SEATING PLANE
VIEW S T L -M
S
T L -M
S
N
S
N
S
NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 -- 0.025 -- 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 -- 0.020 2 10 0.710 0.730 0.040 --
MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.57 4.20 2.79 2.29 0.48 0.33 1.27 BSC 0.81 0.66 -- 0.51 -- 0.64 19.05 19.20 19.05 19.20 1.21 1.07 1.21 1.07 1.42 1.07 0.50 -- 10 2 18.04 18.54 1.02 --
MOTOROLA FAST SRAM
MCM67C518 11
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM67C518 12
CODELINE TO BE PLACED HERE
*MCM67C518/D*
MCM67C518/D MOTOROLA FAST SRAM

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